(1) Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method of the same. In particular, the present invention relates to a semiconductor device in which two or more kinds of field-effect transistors having different threshold voltages are integrated on a compound semiconductor substrate, and to a manufacturing method of the same.
(2) Description of the Related Art
Field-effect transistors made of GaAs (hereinafter referred to as GaAsFET) formed on semiconductor substrates have been used as power amplifiers or switches of communication equipment such as mobile telephone terminals due to its high performance. Particularly, monolithic microwave integrated circuits in which active elements such as a GaAsFET and passive elements such as a resistance element and a capacitance element are integrated (hereinafter referred to as GaAsMMIC) have been widely and practically used.
In recent years, higher function and higher performance are required in the GaAsMMIC. In such a situation, it is desired to have a GaAsMMIC incorporating the power amplifier and the switch including a depression-mode FET (hereinafter referred to as D-FET) and a logic circuit including an enhancement-mode FET (hereinafter referred to as E-FET), that is, an E/D-FET in which the E-FET and the D-FET are mounted in a mixed manner on the identical substrate.
As a conventional E/D-FET, a semiconductor device described in Japanese Unexamined Patent Application Publication No. 8-116034 and a semiconductor device described in Japanese Unexamined Patent Application Publication No. 5-121451 have been known, for example.
Hereinafter, such a conventional E/D-FET is described. First, the conventional semiconductor device disclosed in Japanese Unexamined Patent Application Publication No. 8-116034 is described.
FIG. 1 is a cross-sectional view showing a structure of the semiconductor device described in Japanese Unexamined Patent Application Publication No. 8-116034.
A semiconductor device 400 shown in FIG. 1 includes an E-FET region 41 in which an E-FET is formed and a D-FET region 42 in which a D-FET is formed. The semiconductor device 400 includes a substrate 401 made of a semi-insulating GaAs, a buffer layer 402, a channel layer 403, a donor layer (also referred to as a donor supply layer) 404, a threshold control layer 405, an etching-stopper layer 406, a contact layer 407, an isolation region 408, an insulating film 409, a sidewall protection film 412, gate electrodes 413 and 414, and ohmic electrodes 415.
The buffer layer 402, made of undoped GaAs, is formed on the substrate 401.
The channel layer 403, made of undoped InGaAs, is formed on the buffer layer 402.
The donor layer 404, made of n-type AlGaAs, is formed on the channel layer 403.
The threshold control layer 405, made of n-type AlGaAs, is formed on the donor layer 404.
The etching-stopper layer 406, made of n-type AlGaAs, is formed on the threshold control layer 405.
The contact layer 407, made of n-type GaAs, is formed on the etching-stopper layer 406.
The isolation region 408 is formed by ion implantation, which electrically isolates the E-FET region 41 from the D-FET region 42.
The insulating film 409 is formed on the contact layer 407.
The sidewall protection film 412, made of SiO2, isolates the contact layer 407 from the gate electrode 413 or 414.
The gate electrode 413 contacts the threshold control layer 405 and the etching-stopper layer 406, and forms a Schottky barrier junction with the donor layer 404.
The gate electrode 414 forms a Schottky barrier junction with the etching-stopper layer 406.
The ohmic electrodes 415 are formed in openings formed in the insulating film 409, each of which is electrically connected to the contact layer 407.
Next, a method of manufacturing the conventional semiconductor device 400 is described. FIGS. 2 to 4 are diagrams showing sectional structures in a manufacturing process of the semiconductor device 400.
First, on the substrate 401 made of a semi-insulating GaAs, the GaAs buffer layer 402, the InGaAs channel layer 403, the AlGaAs donor layer 404, the AlGaAs threshold control layer 405, the AlGaAs etching-stopper layer 406 and the GaAs contact layer 407 are epitaxially grown sequentially by using the MOCVD method, the MBE method or the like. The isolation region 408 is formed by implanting boron ions by using a photoresist mask (not illustrated) to thereby form the E-FET region 41 and the D-FET region 42 (FIG. 2).
Next, the insulating film 409 made of SiO2 is formed, and a predetermined region in the insulating film 409 is dry-etched selectively to the contact layer 407 by using a photoresist mask (not illustrated). Further, the GaAs contact layer 407 is dry-etched selectively to the etching-stopper layer 406 to thereby form the gate openings 410 and 411. Further, an insulating film made of SiO2 is formed and then etched back by dry etching, whereby the sidewall protection film 412 is formed (FIG. 3).
Next, the gateway opening 411 is covered with a photoresist mask (not illustrated), and the AlGaAs etching-stopper layer 406 in the gate opening 410 is wet-etched to thereby expose the AlGaAs threshold control layer 405. The AlGaAs threshold control layer 405 is dry-etched selectively to the donor layer 404. Further, the photoresist pattern is removed and WSi and W are laminated, and dry etching is performed on the laminated WSi and W other than a predetermined region by using a photoresist mask (not illustrated) to thereby simultaneously form the E-FET gate electrode 413 and the D-FET gate electrode 414 (FIG. 4).
Next, a predetermined region of the insulating film 409 is opened by using a photoresist mask (not illustrated), and the ohmic electrode 415 made of AuGeNi is formed by the vacuum evaporation and lift-off method. Through the steps described above, the structure of the conventional semiconductor device 400 shown in FIG. 1 is formed.
Next, the conventional semiconductor device disclosed in Japanese Unexamined Patent Application Publication No. 5-121451 is described.
FIG. 5 is a cross-sectional view showing a structure of the semiconductor device described in Japanese Unexamined Patent Application Publication No. 5-121451.
A semiconductor device 500 shown in FIG. 5 includes an E-FET region 51 in which an E-FET is formed, and a D-FET region 52 in which a D-FET is formed. The semiconductor device 500 includes a substrate 501 made of semi-insulating GaAs, a channel layer 502, a donor layer 503, cap layers 504, 505 and 506, an isolation region 507, an insulating film 508, ohmic electrodes 509, and gate electrodes 512 and 513.
The channel layer 502, made of undoped GaAs, is formed on the substrate 501.
The donor layer 503, made of n-type InGaP, is formed on the channel layer 502. The thickness d1 of the donor layer 503 of the E-FET region 51 is formed to be thinner compared with the thickness d2 of the donor layer 503 of the D-FET region 52.
The cap layer 504, made of undoped GaAs, is formed on the donor layer 503.
The cap layer 505, made of n-type InGaP, is formed on the cap layer 504.
The cap layer 506, made of n-type GaAs, is formed on the cap layer 505.
The isolation region 507 is formed by ion implantation, which electrically isolates the E-FET region 51 from the D-FET region 52.
The insulating film 508 is formed on the cap layer 506.
The ohmic electrodes 509 are formed in the openings formed in the insulating film 508, each of which is electrically connected to the cap layer 506.
The gate electrode 512 is formed in the opening formed in the insulating film 508 and the cap layers 504 to 506 of the E-FET region 51, and forms a Schottky barrier junction with the donor layer 503.
The gate electrode 513 is formed in the opening formed in the insulating film 508 and the cap layers 504 to 506 of the D-FET region 52, and forms a Schottky barrier junction with the donor layer 503.
Next, a method of manufacturing the semiconductor device 500 is described. FIGS. 6 and 7 are diagrams showing sectional structures in a manufacturing process of the semiconductor device 500.
First, on the substrate 501 made of semi-insulating GaAs, the GaAs channel layer 502 and the InGaP donor layer 503 are formed sequentially by using the MOCVD method or the MBE method. By using a photoresist mask (not illustrated), the thickness of a part in a predetermined region of the InGaP donor layer 503 is wet-etched. After removing the photoresist mask, the GaAs cap layer 504, the InGaP cap layer 505 and the GaAs cap layer 506 are further formed sequentially. Further, the isolation region 507 is formed by implanting O2 ions by using a photoresist mask (not illustrated) to thereby form the E-FET region 51 and the D-FET region 52 (FIG. 6).
Next, the insulating film 508 made of SiO2 is formed, and a predetermined region is wet-etched selectively to the GaAs cap layer 506 by using a photoresist mask (not illustrated). Further, the ohmic electrodes 509 made of AuGe/Au, making an ohmic contact with the GaAs cap layer 506, are formed by the vacuum evaporation and lift-off method (FIG. 7).
Next, a predetermined region of the insulating film 508 is wet-etched selectively to the GaAs cap layer 506 by using a photoresist mask (not illustrated) to thereby form gate openings for forming the gate electrodes 512 and 513. The GaAs cap layer 506 in the gate opening is wet-etched selectively to the InGaP cap layer 505 to thereby expose the InGaP cap layer 505. Next, the InGaP cap layer 505 is wet-etched selectively to the GaAs cap layer 504 to thereby expose the GaAs cap layer 504. Next, the GaAs cap layer 504 is dry-etched selectively to the InGaP donor layer 503 to thereby expose the InGaP donor layer 503. Further, the E-FET gate electrode 512 and the D-FET gate electrode 513 are formed by means of the vacuum evaporation and lift-off method using Ti/Pt/Au material. Through the steps described above, the structure of the semiconductor device 500 shown in FIG. 5 is formed.